The present invention relates to integrated circuits having two or more embedded processor cores, and more particularly to an interlocutor system and method for allowing one embedded processor core to control operation of a second embedded processor core during at-speed testing of the second core.
An increasing number of systems-on-a-chip are in use having at least two embedded processor cores which share the same external memory interface. These cores commonly include a microcontroller and digital signal processor (DSP) or two DSP cores requesting access to external memory for an instruction or data read/write. The cores may also include microprocessors or other processing devices.
An exemplary system-on-a-chip architecture is illustrated in FIG. 1. As shown in FIG. 1. a single integrated circuit 10 includes a microprocessor 12, DSP 14, and an arbiter 16, and is connected to an external memory device 8. The arbiter 16 determines when access is granted for the microprocessor 12 or DSP 14 to the external memory 8. The microprocessor 12 and DSP 14 send request signals to the arbiter 16 when they need to interface with the external memory 8, and the arbiter 16 sends signals acknowledging these requests.
Outputs from the microprocessor 12 and DSP 14, which includes data signals and address and control signals, are coupled to external memory interface multiplexers 20, which are controlled by a processor selection signal from the arbiter 16. The arbiter 16 determines which processor output is transmitted to the external memory 8 through an output buffer gate or amplifier 22 selectively enabled with an output enable signal. Data retrieved from the external memory 8 is shunted to both processors 12, 14 through an input buffer gate or amplifier 24 for use by one of the processors depending upon the address data.
When being tested, both processor cores 12, 14 need to access instructions and data from the external memory interface, if no on-chip memory exists. Tester loads are usually much greater than the loads normally driven by a chip in application boards. The external memory interface in a testing environment is thus overloaded by a tester, as comparing to the normal on-board applications. As a result, testing cannot be run at the same speed as in applications. Indeed, known testing techniques of embedded microcontrollers employ reduced operating frequencies in order to allow sufficient time for the microcontroller to drive the associated tester loads.
If one of the cores has access to on-chip memory, this memory can be downloaded prior to testing, and test for this core can be performed at speed with subsequent upload of the results from on-chip memory to a tester. If the second core is not associated with on-chip memory, however, its testing still has to be performed at a lower speed or with a greater number of wait states from external memory than normally used in applications.
There is thus a need for a system which allows for at-speed testing of an embedded processor core on a system-on-a-chip.